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Altera_Forum
Honored Contributor
Honored ContributorPLL comensate issue
Hi dears: I am using ArriaGX devices. For some reason, the FPGA only has one input clock, which is input from one of the FPGA's transceiver reference clock pins. So when I implement pll in...
Altera_ForumHonored Contributor
Honored ContributorHi Rysc:
Thanks for your reply. Are the transceiver (GXB) block's reference clock input pins not didecated clock pins? We know these pins supply ref clk for the GXB. Can you tell me what positon we need compenstation for the pll?!
