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Altera_Forum
Honored Contributor
17 years agoPLL comensate issue
Hi dears: I am using ArriaGX devices. For some reason, the FPGA only has one input clock, which is input from one of the FPGA's transceiver reference clock pins. So when I implement pll in...
Altera_Forum
Honored Contributor
17 years agoThe compensation is basically the idea that it's compensating from the clock input to the clock destination. This clock is recovered from a transceiver, and so the whole delay from the transceiver to the PLL is not compensated. Now, in your case that makes perfect sense and you really don't care. The warning is more for the person who brings the clock in on a pin that doesn't directly feed the PLL and thinks they'll get timing as if it were on a dedicated clock input that feeds the PLL. (For example, you get good Tco times. But in your case Tcos don't make sense by themself, since there is no true reference for the clock). Basically you can ignore this warning.