Honored ContributorHello,
Given a design in verilog, is it possible to view the routing information of my design on an fpga? What I'm after is placement information (which LE blocks are connected to eachother) and routing data (which tracks and interconnect switches are used to connect the logic element blocks)
Honored ContributorYou can use the "chip planner" under the tools menu or if you just want to see the logical hookups the "technology map viewer" under tools->netlist viewers
Hope that helped BorisHonored ContributorThanks for the reply,
The chip planner tells me too little information about the routing. I require track number and interconnect switch coordinates. Chip planner is fine for LAB location, but for routing, it tells me nothing except for which blocks are connected to eachother.Honored ContributorNo there is an option called show physical routing .
It will show you the total hops and how actually the routing was done. Now even if you want more then during report timing by time quest enable the option show_routing_details and it will show you the whole routing in the timing reports. Good luckHonored ContributorThanks for the reply, but I'm confused.
Is there an option called "show physical routing"? If so, where is it? I'm unable to find documentation on this feature.Honored ContributorWell i wish i could maybe by monday i will surely..but to guide you...whenyou have opened the chip planner den look towards bottm and towards right not extreme bottom and extreme right jus beneath the fpga structure in chip planner...its easily visible ...i can give u d screen shot by monday..but now its not possible for me..but try to find it...it can be located easily..its not in any tool bar..jus towards right bottom not extreme...
Good luck
