Forum Discussion
Altera_Forum
Honored Contributor
14 years agoplace and route data output
Hello, Given a design in verilog, is it possible to view the routing information of my design on an fpga? What I'm after is placement information (which LE blocks are connected to eacho...
Altera_Forum
Honored Contributor
14 years agoWell i wish i could maybe by monday i will surely..but to guide you...whenyou have opened the chip planner den look towards bottm and towards right not extreme bottom and extreme right jus beneath the fpga structure in chip planner...its easily visible ...i can give u d screen shot by monday..but now its not possible for me..but try to find it...it can be located easily..its not in any tool bar..jus towards right bottom not extreme...
Good luck