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Altera_Forum's avatar
Altera_Forum
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14 years ago

place and route data output

Hello, Given a design in verilog, is it possible to view the routing information of my design on an fpga? What I'm after is placement information (which LE blocks are connected to eacho...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

You can use the "chip planner" under the tools menu or if you just want to see the logical hookups the "technology map viewer" under tools->netlist viewers

Hope that helped

Boris