Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Pin constrain in sdc file

I have not make a FPGA design in Altera device for a while. Just have a question to double check, does Altera improve the functionality of sdc file that now we can put the pin constrains in the sdc file ？ I remember previously we need put pin assignments in another file.

Thanks in advance.

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    By "pin constrains" do you mean pin locations?

    Timing constraints go in the sdc file.

    Pin location constraints go in the project's qsf file.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    By "pin constrains" do you mean pin locations?

    Timing constraints go in the sdc file.

    Pin location constraints go in the project's qsf file.

    Cheers,

    Alex

    --- Quote End ---

    Thanks. But may I put the pin locations in sdc file?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    Thanks. But may I put the pin locations in sdc file?

    --- Quote End ---

    But whyyyyyy? sdc is for timing, not for pins... Synopsis Design Constraints, try and see for yourself
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    One, and only one, qsf file per project.

    Cheers,

    Alex

    --- Quote End ---

    Thanks a lot.