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Altera_Forum
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11 years ago

Pin constrain in sdc file

I have not make a FPGA design in Altera device for a while. Just have a question to double check, does Altera improve the functionality of sdc file that now we can put the pin constrains in the sdc f...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

By "pin constrains" do you mean pin locations?

Timing constraints go in the sdc file.

Pin location constraints go in the project's qsf file.

Cheers,

Alex