Forum Discussion

Honored Contributor

11 years ago

Pin constrain in sdc file

I have not make a FPGA design in Altera device for a while. Just have a question to double check, does Altera improve the functionality of sdc file that now we can put the pin constrains in the sdc f...

Altera_Forum

Honored Contributor

11 years ago

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But whyyyyyy? sdc is for timing, not for pins... Synopsis Design Constraints, try and see for yourself

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I just saw a website mentioned this.

http://www.altera.com/support/software/eda_maxplus2/synplty/intro/pin.html

OK, I can write tcl in qsf to do the pin constrains. For one project, I can only have on qsf file, correct?

Thanks.

Forum Discussion

Pin constrain in sdc file

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