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Altera_Forum's avatar
Altera_Forum
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13 years ago

Phase relationship between 2 different PLL with the same source

Hi everyone,

I've got a question :

1 - I have 2 PLLs with the same input clock (80 MHz) coming from the same pin.

2 - Both PLL generate a bunch of clocks, but both generate a 20 MHz clock (20% duty cycle, for the 1st PLL) and 25% duty cycle for the second PLL.

3 - The PLL are in normal mode (I've tried source-synchronous too)

Here's what happens

The phase relationship between the two 20 MHz clocks change from power-up to power-up. Both edge should occur at the same time. However, in one power-up the delay between the 2 edges can be 20 ns, the next one 10 ns, etc.

Do you guys have any idea what can cause this? Is this supposed to be happening? I'm thinking that maybe my clock source isn't clean enough at start-up and that I should wait a few milliseconds and then reset both PLLs. Do you have other suggestions and or workarounds?

I cannot use only one PLL since I have too many clock outputs to generate and they need to have a known phase relation.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I will expect variable delay between ref clk pin and the two PLLs as well as between PLL outputs and their pins. But powerup variation is another issue that may be related to your measurement setup or io jitter.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    A PLL is specified to start after a reset with defined input to output phase relation. To assure this, the reset must be released after the input clock is established, or self-reset with loss-of-lock must specified.

    By nature of PLL operation, the fixed phase relation is achieved according to the input clock and can only span one input clock period. If you have multiple PLLs generating the same frequency fin/N, their phase can be different in steps of 1/fin (12.5 ns in your case).

    There are different ways to overcome the problem, e.g. cascading PLLs, using a lower internal reference frequency.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I believe this is expected with divided down clocks. How come you have two clocks of the same frequency? Some thoughts:

    Can you move them both to the same PLL, which will be in aligned?

    Can you put the 20MHz logic into the 80MHz domain and use a clock enable?

    I wrote a synchronization circuit to try and match clocks across different PLLs in different FPGAs, but it's kind of a pain(it uses the altclkctrl enable function to divide down the clock), but I'm wondering if there's an easier way...

    http://www.alteraforum.com/forum/showthread.php?t=1564