Phase relationship between 2 different PLL with the same source

A PLL is specified to start after a reset with defined input to output phase relation. To assure this, the reset must be released after the input clock is established, or self-reset with loss-of-lock must specified.

By nature of PLL operation, the fixed phase relation is achieved according to the input clock and can only span one input clock period. If you have multiple PLLs generating the same frequency fin/N, their phase can be different in steps of 1/fin (12.5 ns in your case).

There are different ways to overcome the problem, e.g. cascading PLLs, using a lower internal reference frequency.