Agilex 5E: HPS2FPGA access to FPGA-side DDR4 EMIF

Hi,

I am working with an Agilex 5E GSRD-based design and would like to use the FPGA-side DDR4 as the data buffer for an FPGA accelerator.

The intended data path is:

HPS/ARM → HPS2FPGA bridge → FPGA-side DDR4 EMIF → FPGA accelerator

The FPGA accelerator would also read and write the same DDR4 through the EMIF AXI interface.

So far, I have verified the following:

1. HPS2FPGA access to FPGA on-chip memory works.
2. The FPGA-side DDR4 EMIF passes the JTAG/pattern test from the example design.
3. However, when I connect HPS2FPGA to the DDR4 EMIF AXI interface and try to access it from Linux, the access fails with a bus error / SError.

My question is:

Is it expected to be supported for the HPS to directly access FPGA-side DDR4 through HPS2FPGA on Agilex 5E, while an FPGA IP also accesses the same DDR4 through the EMIF AXI interface?

If yes, are there any required Platform Designer connections, bridge settings, address map settings, or arbitration/interconnect requirements that I should check?

I can provide the Platform Designer screenshot, address map, and error log if helpful. I actually provided more details, but whenever I posted them on the forum, the system kept automatically marking my post as spam, even though I honestly don’t understand what part of it looked like spam.

Thank you!