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Altera_Forum
Honored Contributor
Honored ContributorPhase relationship between 2 different PLL with the same source
Hi everyone, I've got a question : 1 - I have 2 PLLs with the same input clock (80 MHz) coming from the same pin. 2 - Both PLL generate a bunch of clocks, but both generate a 20 MHz cl...
Altera_ForumHonored Contributor
Honored ContributorI will expect variable delay between ref clk pin and the two PLLs as well as between PLL outputs and their pins. But powerup variation is another issue that may be related to your measurement setup or io jitter.
