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Altera_Forum
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13 years ago

Phase relationship between 2 different PLL with the same source

Hi everyone, I've got a question : 1 - I have 2 PLLs with the same input clock (80 MHz) coming from the same pin. 2 - Both PLL generate a bunch of clocks, but both generate a 20 MHz cl...
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Altera_Forum
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13 years ago

I believe this is expected with divided down clocks. How come you have two clocks of the same frequency? Some thoughts:

Can you move them both to the same PLL, which will be in aligned?

Can you put the 20MHz logic into the 80MHz domain and use a clock enable?

I wrote a synchronization circuit to try and match clocks across different PLLs in different FPGAs, but it's kind of a pain(it uses the altclkctrl enable function to divide down the clock), but I'm wondering if there's an easier way...

http://www.alteraforum.com/forum/showthread.php?t=1564