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Altera_Forum
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16 years ago

PCS mandatory for Inter Transceiver Block synchronisation ?

My current design consists in interfacing a high-speed ADC (18-bit@2Gbps) to the Stx IV-GX receiver blocks. The main concern is ADC<->FPGA transceivers synchronisation.

How to make sure all the 18 parallel bits of a sample are captured synchronously and aligned when delivered to the FPGA fabric?

My very first plan was to have the cheapest and most simple implementation by using 18 basic PMA-only channels but reading the StxIV device handbook, there is not a word about the synchronisation state of the PMA deserializers after a power-up and reset sequence.

Does it mean I can’t bypass the PCS ? Is it mandatory to use either the PCS word aligner blocks and/or the deskew FIFO and/or the RX phase compensation FIFO in order to make sure all the captured serial bits belong to the same sample and are aligned at the deserializer parallel data output ?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi Oli,

    Did you manage to get this working? I have a similar synchronization problem with a 5-bit ADC. I want to capture the 5 bitstreams with the receiver at the same time. But it seems like every time the receivers power up, they have different latencies.

    Let me know if you managed to figure this out.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Is there anything in the ADC data that would allow you to align the data? Are the ADC outputs encoded (8b10b or something)?

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi Jake, thanks for the reply.

    The ADC outputs aren't necessarily encoded, they're just whatever comes out of the ADC. Is there any information on what kind of data transition density is needed for the CDR to recover the clock?

    I realize 8B10B encoding would be good, but what if there were only guaranteed transitions every 32 bits? Every 128 bits?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Well you're certainly not making things easy for the CDR. Are you AC or DC coupled between the ADC and FPGA?

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    AC coupled, which could also limit the minimum transition density depending on how big the capacitor is. But I think the CDR would probably be the limiting factor.

    If it can't handle (say) 32 bits in a row with no transitions, I guess that would mean its sampling phase may be off until the transitions start coming again. Then the first few bits may be sampled incorrectly before the CDR is able to lock again.