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Altera_Forum
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16 years ago

PCS mandatory for Inter Transceiver Block synchronisation ?

My current design consists in interfacing a high-speed ADC (18-bit@2Gbps) to the Stx IV-GX receiver blocks. The main concern is ADC<->FPGA transceivers synchronisation. How to make sure all the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi Oli,

Did you manage to get this working? I have a similar synchronization problem with a 5-bit ADC. I want to capture the 5 bitstreams with the receiver at the same time. But it seems like every time the receivers power up, they have different latencies.

Let me know if you managed to figure this out.