Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

PCS mandatory for Inter Transceiver Block synchronisation ?

My current design consists in interfacing a high-speed ADC (18-bit@2Gbps) to the Stx IV-GX receiver blocks. The main concern is ADC<->FPGA transceivers synchronisation. How to make sure all the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

AC coupled, which could also limit the minimum transition density depending on how big the capacitor is. But I think the CDR would probably be the limiting factor.

If it can't handle (say) 32 bits in a row with no transitions, I guess that would mean its sampling phase may be off until the transitions start coming again. Then the first few bits may be sampled incorrectly before the CDR is able to lock again.