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Altera_Forum
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16 years ago

PCS mandatory for Inter Transceiver Block synchronisation ?

My current design consists in interfacing a high-speed ADC (18-bit@2Gbps) to the Stx IV-GX receiver blocks. The main concern is ADC<->FPGA transceivers synchronisation. How to make sure all the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Is there anything in the ADC data that would allow you to align the data? Are the ADC outputs encoded (8b10b or something)?

Jake