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Altera_Forum
Honored Contributor
Honored ContributorPCS mandatory for Inter Transceiver Block synchronisation ?
My current design consists in interfacing a high-speed ADC (18-bit@2Gbps) to the Stx IV-GX receiver blocks. The main concern is ADC<->FPGA transceivers synchronisation. How to make sure all the...
Altera_ForumHonored Contributor
Honored ContributorHi Jake, thanks for the reply.
The ADC outputs aren't necessarily encoded, they're just whatever comes out of the ADC. Is there any information on what kind of data transition density is needed for the CDR to recover the clock? I realize 8B10B encoding would be good, but what if there were only guaranteed transitions every 32 bits? Every 128 bits?
