Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

PCS mandatory for Inter Transceiver Block synchronisation ?

My current design consists in interfacing a high-speed ADC (18-bit@2Gbps) to the Stx IV-GX receiver blocks. The main concern is ADC<->FPGA transceivers synchronisation. How to make sure all the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi Jake, thanks for the reply.

The ADC outputs aren't necessarily encoded, they're just whatever comes out of the ADC. Is there any information on what kind of data transition density is needed for the CDR to recover the clock?

I realize 8B10B encoding would be good, but what if there were only guaranteed transitions every 32 bits? Every 128 bits?