Output Voltage Higher than Maximum Voltage of GPIO
Dear all,
I have written a code that sends out a PWM signal with a duty cycle of 50% at 12.5 MHz. I am using the DE10-Lite board with the MAX 10 FPGA and Quartus 23.1.1 software on Windows 11. When I uploaded the code and observed the signal through an oscilloscope, I found that the overshoot of the signal reached a maximum value of 4.76V. How would this be possible when I assigned a 3.3V LVTTL pin as the output with a current of 8amps? I tried lowering current to 4 amps, assigning different pin locations, with no success. I also sampled the PWM at a lower frequency of 3KHz, and observed that it still had an overshoot to 4.76V. As well as using a multimeter to detect the output voltage at the GPIO, where I measured a level of approx. 2.5V, which should not be the case as the measured voltage should 50% of 3.3V, e.g. 1.666V.
I have attached the picture of the oscilloscope, where orange is the PWM signal and blue is another PWM signal which is the "NOT" version.
Anybody have any idea what could be the case?