Forum Discussion
Luckyguide
New Contributor
New ContributorOutput Voltage Higher than Maximum Voltage of GPIO
Dear all, I have written a code that sends out a PWM signal with a duty cycle of 50% at 12.5 MHz. I am using the DE10-Lite board with the MAX 10 FPGA and Quartus 23.1.1 software on Windows 11. When ...
FvM
Super Contributor
Super ContributorHi,
I believe it's a measurement artifact in the first place, as guessed before. Unfortuantely it's hard to decide about the original waveform without probe connected. If you don't have suitable active probe, I would design termination and determine expectable signal quality based on analysis of PCB impedances.
