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Altera_Forum's avatar
Altera_Forum
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15 years ago

Output Pins stuck at VCC or GND (All of them!)

Hello

I am using the Altera PCI-compiler MegaCore in 32bit target mode on a Cyclone III EP3C16F484I7.

When I simulated my code in ModelSim (Altera edition), it work perfectly. But when I try to put it on the chip all the output lines are stuck at GND. I can't see any mistakes in my code, is there any special setting I need to know about for compiling the PCI-compiler module? We have a license for it.

The PCI Megacore functions after programming as the device enumerates on the PCI bus, but none of my functionality works as all the (non PCI) pins are stuck at GND.

Any thoughts?

Thanks

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    There are several points to check:

    - pinout report shows the pin actually connected as intended?

    - any warnings during compilation about discarded logic or pins stuck?

    - clock and reset signals applied correctly and with expected polarity
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I've checked the pinouts and they seem correct.

    There are many warnings during compile time, some are expected as some functionality is not yet implemented, hence those pins are allowed to have a stuck at fault. But I also get stuck at warnings for pins that should be functioning, as I said, they simulated as expected.

    There are warnings about VHDL Process Statement warning at Buit-In-Test.vhd(161): signal "mysignal" is read inside the Process Statement but isn't in the Process Statement's sensitivity list.

    This may be a silly question, but do all signals used in a process need to be in the sensitivity list?

    Also how do i resolve the following warnings.

    Warning: (Medium) Rule C106: Clock signal source should not drive registers triggered by different clock edges. Found 1 node(s) related to this rule.

    Warning: Node "CLK"

    and

    Warning: (Medium) Rule R102: External reset signals should be synchronized using two cascaded registers. Found 1 node(s) related to this rule.

    Warning: Node "RSTN"

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    but do all signals used in a process need to be in the sensitivity list?

    --- Quote End ---

    All clocks and asynchronous signals should be included. But omitting them causes only problems in simulation, sensitivity lists are ignored in Quartus synthesis, but wanings are issued though.

    Also the other warnings you quoted won't be expected to cause the reported behaviour.

    This sounds more alarming:

    --- Quote Start ---

    But I also get stuck at warnings for pins that should be functioning

    --- Quote End ---

    But as said, the problem may be also due to signals not present in the hardware or not acting as expected.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks for your help FvM.

    I found the problem, I have a block of logic that is't completed yet, so I'd assumed that it would be fine uninitialized. But I think this allowed the compiler to pick "optimal" values for the uninitialized ports, creating a situation where the rest of my logic was OR'd with 1 meaning it all got optimized away. Thanks