Output Pins stuck at VCC or GND (All of them!)

I've checked the pinouts and they seem correct.

There are many warnings during compile time, some are expected as some functionality is not yet implemented, hence those pins are allowed to have a stuck at fault. But I also get stuck at warnings for pins that should be functioning, as I said, they simulated as expected.

There are warnings about VHDL Process Statement warning at Buit-In-Test.vhd(161): signal "mysignal" is read inside the Process Statement but isn't in the Process Statement's sensitivity list.

This may be a silly question, but do all signals used in a process need to be in the sensitivity list?

Also how do i resolve the following warnings.

Warning: (Medium) Rule C106: Clock signal source should not drive registers triggered by different clock edges. Found 1 node(s) related to this rule.

Warning: Node "CLK"

and

Warning: (Medium) Rule R102: External reset signals should be synchronized using two cascaded registers. Found 1 node(s) related to this rule.

Warning: Node "RSTN"

Thanks