Forum Discussion
Altera_Forum
Honored Contributor
15 years agoThanks for your help FvM.
I found the problem, I have a block of logic that is't completed yet, so I'd assumed that it would be fine uninitialized. But I think this allowed the compiler to pick "optimal" values for the uninitialized ports, creating a situation where the rest of my logic was OR'd with 1 meaning it all got optimized away. Thanks