`define DZERO_GREATER 2
`define ADC_CONVST_CYCLES ( 10 - `DZERO_GREATER )
`define WAIT_CYCLES 5
`define TRANSFER_CLOCKS (12)
`define SCK_ON ( `ADC_CONVST_CYCLES + `WAIT_CYCLES )
`define SCK_OFF ( `SCK_ON + `TRANSFER_CLOCKS )
`define SHIFT_OFF (`SCK_ON + 6 )
module ltc2308 (
clk,go,ADC_SDO,chansel,
ADC_CONVST,ADC_SCK,ADC_SDI,done,data
);
input clk,go,ADC_SDO;
input [3:0] chansel;
output ADC_CONVST,ADC_SCK,done;
output reg ADC_SDI;
output reg[11:0] data;
////////////////////////////////////////////////////////////////////////
//Generates negative reset_p pulse signal at go signal posedge.
////////////////////////////////////////////////////////////////////////
wire resetp;
reg rstbegin;
assign resetp = ( (rstbegin == 1'b0) && (go == 1'b1) )? 1'b0 : 1'b1;
always@(posedge clk) begin
rstbegin <= go;
end
////////////////////////////////////////////////////////////////////////
//CFG bits at resetp
////////////////////////////////////////////////////////////////////////
reg [5:0] cmd;
always@(negedge resetp) begin
cmd <= { chansel, 2'b10};
end
////////////////////////////////////////////////////////////////////////
//Cycle counter
////////////////////////////////////////////////////////////////////////
reg [7:0] counter;
assign ADC_CONVST = (counter>`ADC_CONVST_CYCLES)? 1'b0 : 1'b1;
always@(posedge clk or negedge resetp) begin
if(resetp==1'b0)
counter <= 8'b0;
else if(done == 1'b0)
counter <= counter + 1'b1;
end
////////////////////////////////////////////////////////////////////////
//SCK
////////////////////////////////////////////////////////////////////////
reg sckon;
assign ADC_SCK = (sckon==1'b1)? clk : 1'b0;
always@(negedge clk or negedge resetp) begin
if(resetp==1'b0)
sckon <= 1'b0;
else if ( (counter>=`SCK_ON && counter<`SCK_OFF) )
sckon <= 1'b1;
else
sckon <= 1'b0;
end
////////////////////////////////////////////////////////////////////////
//RX
////////////////////////////////////////////////////////////////////////
reg [3:0] irx;
assign done = (irx > (`TRANSFER_CLOCKS - 1) )? 1'b1 : 1'b0;
always@(negedge clk or negedge resetp) begin
if(resetp==1'b0) begin
data <= 12'b0;
irx <= 4'b0;
end
else if ( sckon == 1'b1 ) begin
irx <= irx + 1'b1;
data[11-irx] <= ADC_SDO;
end
end
////////////////////////////////////////////////////////////////////////
//TX
////////////////////////////////////////////////////////////////////////
reg [2:0] itx;
always@(negedge clk or negedge resetp) begin
if(resetp==1'b0) begin
itx <= 3'b0;
ADC_SDI <= 1'b0;
end
else if ( (counter >= `SCK_ON) && (counter < `SHIFT_OFF) ) begin
itx <= itx + 1'b1;
ADC_SDI <= cmd[5-itx]; end
else
ADC_SDI <= 1'b0;
end
endmodule
what means "time compensated design" ?
I use vga because it´s easy to find a cheap "second hand" monitor for use with fpga and almost all people haves one vga monitor ...
But i will add hdmi too !!
I like qsys so much i enjoy a lot designing my own system i love this architecture, now i have a nios on the fpga side and the system its similar to the I.MX6 soloX with the cortexA + cortex M but with a lot of flexibility, i´m designing a board with the cheaper cyclone V soc i found at mouser 5CSEBA2U19C86N
[h=1][/h]
Honored Contributor
