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Hi, it is not really necessary at normal resolution, if you wish have full HD or 4HD then a separate memory is better due memory channel bandwidth reduce processor speed too.
Memory of HPS can be accessed from FPGA and FPGA memory controller can be accessed from HPS too.
Which IP did you used for your design and how are they interconnected on QSYS?
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I wrote the code by hand ! Its not connected to qsys, i have two versions, fifo and axi but now it runs freely without bus connection.
I placed a post in the general topics for asking forum members to a group purchase of mi next evaluation board you can see a picture of the board
I designed a verilog axi slave for acces the adc from linux, it runs fine and you can full configure it, i can pass you the code if you want
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