Output Linux´s Video to VGA controller in FPGA Fabric through AXI on CV SoC

Hi nachodizz990, Hmmm i am not so proficient in Verilog due I am prevalent VHDL developer but at glance this code seems an ADC module interface than video...

About high speed design you need compensate for both impedance and time of fly, all signal must arrive at same time to DDR Chip.

try these if you like video or recommendation about DDR wiring:

in first this is related to RF and High speed, DDR are High speed and if lines impedance is not adapted they become RF transmitters too.

https://www.youtube.com/watch?v=6jrvzu7eqiw

This is a lesson on how to route an High Speed LVDS track.

https://www.youtube.com/watch?v=blhlmq2ho1w

https://www.youtube.com/watch?v=41r3kkm_fme

your tools resemble Altium so check also this on length compensation

https://www.youtube.com/watch?v=bzrdfcjilga

If you like readable document or a book I can post reference.

Regards