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I wrote the code by hand ! Its not connected to qsys, i have two versions, fifo and axi but now it runs freely without bus connection.
I placed a post in the general topics for asking forum members to a group purchase of mi next evaluation board you can see a picture of the board
I designed a verilog axi slave for acces the adc from linux, it runs fine and you can full configure it, i can pass you the code if you want
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Good Idea, just check if this don't infringe forum rules, I am quite new and we need read FAQ or ask moderator, also ask Terasic for, Maybe I got interested to use DE0 Nano instead of DE1_SOC, just a question, why VGA when all new monitor are switching to HDMI?
About code, I can take an eye and try port to QSYS to share if you wish, this can improve the usability of your "cape". (Cape is the add on of Beagle Bone as for shield of arduc and boosterpak of TI, nothing to do with Terasic simply call "Daughter card")
After a long time coding by hand I decided to learn how QSYS work and now a lot of my module are near ported to. It is a valuable tool and save a lot of time on connecting layer.
Some drawback are still on, Linux version is plagued by a bug on graphical and sometimes PLL IP must be edited by hand, this is not a problem, as for Linux when GUI doesn't work or don't know how to I just edit config files script or just do some command line actions.
IMHO switch layer from processor and peripheral can be optimized to reduce silicon usage, but it work and for now things fit on selected size with some small margin.
PS: remember to use time compensated design on PCB artwork.
Honored Contributor
