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Altera_Forum
Honored Contributor
Honored Contributornoise in the signal acquisition
Hi,everyone.
I'm doing some works on signal acquisition based on the FPGA, the quartus report that the fmax is 185Mhz, and i make the clock 180Mhz,but the data converted by the ADC have some noise ,i look it in the signaltap, the FPGA is 3c25, why this is noise? when i make it to be 100Mhz,it works OK.5 Replies
Altera_Forum--- Quote Start --- no solutions yet? --- Quote End --- The original poster didn't report, how he wanted to guarantee a correct timing when reading the ADC output signal. The classical timing analysator offers only limited means to achieve this. A more empirical approach besides specifying the ADC timing correctly with TimeQuest is to implement a phase shifted clock supplying the ADC adjust it for maximum timing margin.- Altera_Forum
no solutions yet?
- Altera_Forum
well, i use the classic timing analyzer,and i set fmax to be 185Mhz,i also set the tsu,tco,th,tpd,and it showed that the fmax of the quartus project is 185Mhz. the Fmax of ADC is 210MSPS(TI ADS5474)
- Altera_Forum
Also, what's the FMAX for the ADC?
- Altera_Forum
Fmax is valid for ADC if you enter the ADC tCO (and board delays) in sdc file correctly. Then check the timing report.
