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Altera_Forum's avatar
Altera_Forum
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15 years ago

noise in the signal acquisition

Hi,everyone. I'm doing some works on signal acquisition based on the FPGA, the quartus report that the fmax is 185Mhz, and i make the clock 180Mhz,but the data converted by the ADC have some noise...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Fmax is valid for ADC if you enter the ADC tCO (and board delays) in sdc file correctly. Then check the timing report.