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Altera_Forum
Honored Contributor
Honored Contributornoise in the signal acquisition
Hi,everyone. I'm doing some works on signal acquisition based on the FPGA, the quartus report that the fmax is 185Mhz, and i make the clock 180Mhz,but the data converted by the ADC have some noise...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- no solutions yet? --- Quote End --- The original poster didn't report, how he wanted to guarantee a correct timing when reading the ADC output signal. The classical timing analysator offers only limited means to achieve this. A more empirical approach besides specifying the ADC timing correctly with TimeQuest is to implement a phase shifted clock supplying the ADC adjust it for maximum timing margin.
