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Altera_Forum
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15 years ago

noise in the signal acquisition

Hi,everyone. I'm doing some works on signal acquisition based on the FPGA, the quartus report that the fmax is 185Mhz, and i make the clock 180Mhz,but the data converted by the ADC have some noise...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

well, i use the classic timing analyzer,and i set fmax to be 185Mhz,i also set the tsu,tco,th,tpd,and it showed that the fmax of the quartus project is 185Mhz. the Fmax of ADC is 210MSPS(TI ADS5474)