No logic elements although I have an output

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Initially, you may do better using the mega wizard to generate the ram, then you know for sure that a ram will be used. Infered ram has to match the correct behavioural template to be correctly inferred, otherwise logic will be inferred.

Review this document for coding styles:

https://people.ece.cornell.edu/land/courses/ece5760/de1_soc/hdl_style_qts_qii51007.pdf

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I didn't call memory using mega wizard before , so I will read the document carefully and try it. I am really thankful to you. You are really helping me.

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Initially, you may do better using the mega wizard to generate the ram, then you know for sure that a ram will be used. Infered ram has to match the correct behavioural template to be correctly inferred, otherwise logic will be inferred.

Review this document for coding styles:

https://people.ece.cornell.edu/land/courses/ece5760/de1_soc/hdl_style_qts_qii51007.pdf

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Dear Admin,

I have created a memory ( but without wizard) and read it as follows

PROCESS (clock)

variable i:integer range -1 to 31:=-1;

BEGIN

IF rising_edge(clock) THEN

i:=i+1;

q1 <= ram1(i); -- output ( ram is mif file of 32 element, each of 3 bits)

END IF;

END PROCESS;

ram1 is external file that I successfully read its data , each element read in one clock cycle.

However , I am trying to get the first three elements after they read to apply a mathematical equation to them in next clock cycle. when I tried to create registers to carry the values , I unintentionally read three element at the same time so the memory transferred to logic elements.

My question is , How can I store only three elements and add them and then I get another three to add while keep reading? I tried to postponed in this way but am not sure if its true

BEGIN

IF rising_edge(clock) THEN

i:=i+1;

reg1 <= ram1(i);

reg2<=reg1;

reg3<=reg2;

q1<=reg3;

I highly suggest reading how memory works. You can only access 1 address per clock cycle. So if you really want to access 3 elements to add them, you will have to read them out over 3 clock cycles. You could pipeline the design to do the adds to minimise total latency.

I highly suggest using the megawizard ram, as this would become obvious.

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I highly suggest reading how memory works. You can only access 1 address per clock cycle. So if you really want to access 3 elements to add them, you will have to read them out over 3 clock cycles. You could pipeline the design to do the adds to minimise total latency.

I highly suggest using the megawizard ram, as this would become obvious.

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When I create a wizard I don't see how to connect it with my vhdl code in Pedroni book or in the document you sent me.

Also, I wonder if this way of reading in three clock cycles is efficient way

IF rising_edge(clock) THEN

i:=i+1;

reg1 <= ram1(i);

reg2<=reg1;

reg3<=reg2;

q1<=reg3;

Or you suggest me better one?

Thanks alot

Your code still suggests you think you're writing software. You are not. You need to understand how the hardware works before you should be writing the code - hence why I suggest drawing a diagram.

I suggest reading how the ram works from here:

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_ram.pdf

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Your code still suggests you think you're writing software. You are not. You need to understand how the hardware works before you should be writing the code - hence why I suggest drawing a diagram.

I suggest reading how the ram works from here:

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_ram.pdf

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Ok. I will .

Thank you.