Hello Please guide me why I don't see any logic element for the current code : LIBRARY ieee; USE ieee.std_logic_1164.all; Use ieee.numeric_std.all; USE work.my_data_types.all; -- to define array of input ( package ) ENTITY test IS PORT ( clk: in std_logic; OutResult: out signed(9 downto 0)); end test; Architecture behave of test is Signal Im : Array2D:=(("0010000111","0001111110","0001001101","0000000000","0000000000"), ("0001001111","0010000100","0000101100","0000011011","0000000000"), ("0001011101","0010000100","0000100111","0000101001","0000000000"), ("0001011101","0010000100","0000100111","0000101001","0000000000"), ("0000000000","0000000000","0000000000","0000000000","0000000000")); signal Bufftemp:Array2D; signal Buffsig:signed(9 DOWNTO 0); begin Process (clk) variable i,j:integer range 0 to 7:=0; begin if (clk' event and clk='1') then for j in 0 to 1 loop for i in 0 to 1 loop Bufftemp(2*j,2*i+1)<= Im(2*j,2*i+1) - 5; end loop; end loop; end if; Buffsig<=Bufftemp(i,j); end process; OutResult<=Buffsig; end behave;

This will because buffsig is a constant. i and j are always 0 when assigning buffsig. And all buffsig values are assigned from a constant. So hence the design is reduced to a constant driver.

You misunderstand for loops. The loops are evaluated completely each clock cycle. The code outputs constantly the last array element. No logic cells required.

Thank you very much Tricky and FvM. I am really appreciate your instant help. I figured out a solution to read one element each clock cycle as listed as I see it best solution Process (clk) variable i,j:integer range 0 to 7:=0; begin i:=i+1; if i=7 then i:=0; j:=j+1; end if; if (clk' event and clk='1') then Bufftemp(2*j,2*i+1)<= Im(2*j,2*i+1) - 5; Buffsig<=Bufftemp(i,j); OutResult<=Buffsig; end if; end process;

I highly suggest reading books or tutorials on using VHDL for digital logic design. Here you have code that doesnt fit with normal templates. It may "work" in hardware as Quartus tends to let you get away with some poor coding styles, but your code will likely appear a but strange in simulation. 1. First of all, I highly suggest you only use signals for the time being, at least until you understand the consequences of using variables on your inferred hardware. 2. You i and j counters are not inside the clocked part of the process, so in simulation they will count on both the rising and falling edges of the clock, which is not possible in real hardware. This is because of the way VHDL works. These should be moved inside the rising edge clock part. 3. While it is not a "bad" thing, do you realise you have a 3 clock latency through the design? Have you tried to simulate this in a simulator? like modelsim?

--- Quote Start --- I highly suggest reading books or tutorials on using VHDL for digital logic design. Here you have code that doesnt fit with normal templates. It may "work" in hardware as Quartus tends to let you get away with some poor coding styles, but your code will likely appear a but strange in simulation. 1. First of all, I highly suggest you only use signals for the time being, at least until you understand the consequences of using variables on your inferred hardware. 2. You i and j counters are not inside the clocked part of the process, so in simulation they will count on both the rising and falling edges of the clock, which is not possible in real hardware. This is because of the way VHDL works. These should be moved inside the rising edge clock part. 3. While it is not a "bad" thing, do you realise you have a 3 clock latency through the design? Have you tried to simulate this in a simulator? like modelsim? --- Quote End --- Dear Moderator , I will consider all your points , Actually I read books for Pedroni and Pong about VHDL programming , I know I still have a lot to learn since I unconsciously back to sequential programming I used to utilize. About your notes, I will move the counters , this point I got it clearly. -- About signals , I will use them and hopefully you guide me to certain book that I can have better understanding. --Modelsim is not work often with my designs ! I am using Quartus ! Finally about the latency , I am thinking of unnecessary statement of signal assignment , but this will costs 1 clock cycle .. where is the other two? Dear, I am really appreciate your help and reply , I have designed an algorithm but I know I am unable to implement it well, as a consequence , each note you give will raise the implementation a lot. And I am ready to read any book you suggest Thanks again.

No logic elements although I have an output

26 Replies

Altera_Forum
Honored Contributor
8 years ago
This will because buffsig is a constant. i and j are always 0 when assigning buffsig. And all buffsig values are assigned from a constant. So hence the design is reduced to a constant driver.
Altera_Forum
Honored Contributor
8 years ago
You misunderstand for loops. The loops are evaluated completely each clock cycle. The code outputs constantly the last array element. No logic cells required.
Altera_Forum
Honored Contributor
8 years ago
Thank you very much Tricky and FvM. I am really appreciate your instant help. I figured out a solution to read one element each clock cycle as listed as I see it best solution

Process (clk)

variable i,j:integer range 0 to 7:=0;

begin
i:=i+1;
if i=7 then
i:=0;
j:=j+1;
end if;

if (clk' event and clk='1') then

Bufftemp(2*j,2*i+1)<= Im(2*j,2*i+1) - 5;

Buffsig<=Bufftemp(i,j);
OutResult<=Buffsig;

end if;

end process;
Altera_Forum
Honored Contributor
8 years ago
I highly suggest reading books or tutorials on using VHDL for digital logic design. Here you have code that doesnt fit with normal templates. It may "work" in hardware as Quartus tends to let you get away with some poor coding styles, but your code will likely appear a but strange in simulation.

1. First of all, I highly suggest you only use signals for the time being, at least until you understand the consequences of using variables on your inferred hardware.
2. You i and j counters are not inside the clocked part of the process, so in simulation they will count on both the rising and falling edges of the clock, which is not possible in real hardware. This is because of the way VHDL works. These should be moved inside the rising edge clock part.
3. While it is not a "bad" thing, do you realise you have a 3 clock latency through the design?

Have you tried to simulate this in a simulator? like modelsim?
Altera_Forum
Honored Contributor
8 years ago
--- Quote Start ---
I highly suggest reading books or tutorials on using VHDL for digital logic design. Here you have code that doesnt fit with normal templates. It may "work" in hardware as Quartus tends to let you get away with some poor coding styles, but your code will likely appear a but strange in simulation.

1. First of all, I highly suggest you only use signals for the time being, at least until you understand the consequences of using variables on your inferred hardware.
2. You i and j counters are not inside the clocked part of the process, so in simulation they will count on both the rising and falling edges of the clock, which is not possible in real hardware. This is because of the way VHDL works. These should be moved inside the rising edge clock part.
3. While it is not a "bad" thing, do you realise you have a 3 clock latency through the design?

Have you tried to simulate this in a simulator? like modelsim?
--- Quote End ---

Dear Moderator ,
I will consider all your points , Actually I read books for Pedroni and Pong about VHDL programming , I know I still have a lot to learn since I unconsciously back to sequential programming I used to utilize. About your notes, I will move the counters , this point I got it clearly.

-- About signals , I will use them and hopefully you guide me to certain book that I can have better understanding.
--Modelsim is not work often with my designs ! I am using Quartus !
Finally about the latency , I am thinking of unnecessary statement of signal assignment , but this will costs 1 clock cycle .. where is the other two?

Dear, I am really appreciate your help and reply , I have designed an algorithm but I know I am unable to implement it well, as a consequence , each note you give will raise the implementation a lot. And I am ready to read any book you suggest
Thanks again.
Altera_Forum
Honored Contributor
8 years ago
The problem I got after removing for statement is that , I have a shared signal which is a 2D array. I assigned values to different cells in each process. But in compilation, Multiple constant assignent error is shown . My question is that , Isn't it possible to assign values to the same array in different processes if the places of assignment are different ?

This is the code if you may...

-- In process 1 :
if (clk' event and clk='1') then
Bufftemp(2*j,2*i+1)<= Im(2*j,2*i+1) - 5;
end if;

-- In process 2 :
if (clk' event and clk='1') then
Bufftemp(2*j,2*i)<= Im(2*j,2*i) - 5;
end if;

Error : Error (10028): Can't resolve multiple constant drivers for net "Bufftemp[0][0][9]"
Altera_Forum
Honored Contributor
8 years ago
Bufftemp(2*j,2*i+1)<= Im(2*j,2*i+1) - 5; Buffsig<=Bufftemp(i,j); OutResult<=Buffsig;

This is 3 clocks to get from i/j values top the outResult. One clock for each assignment.

--- Quote Start ---

-Modelsim is not work often with my designs ! I am using Quartus !

--- Quote End ---

Why not? Maybe there is a problem? isnt that what we are here for?
Quartus only does post synthesis simulation so is very slow and doesnt actually simulate your code, just the compiled version of it. RTL simulation would be much faster when you get to larger designs

Yes, you can assign different elements of an array in different processes IF you are not using a loop.
I suggest looking at the bits in the error.
Or maybe post the whole code so we can help?
Altera_Forum
Honored Contributor
8 years ago
Thank you , This is the code, the 2d image is :
TYPE Array2D IS ARRAY (0 TO 16, 0 TO 16) OF signed(9 DOWNTO 0);

ENTITY AVhdl IS
PORT (
clk: in std_logic;
BuffD_RP1,BuffD_RP0: out vector_array);

end AVhdl;

Architecture behave of AVhdl is

Signal Im : Array2D:=(("0010000111","0001111110","0001001101","0001011011","0001101001","0001101011","0001101001","0001100111","0001101000","0001100000","0001110011","0010000100","0010001111","0010000000","0001100000","0001000100","0000000000"),
("0010000111","0001111010","0001001010","0001011001","0001100110","0001101000","0001110010","0010000001","0001101111","0001011100","0001101001","0010000011","0001111010","0010011000","0001000111","0000010010","0000000000"),
("0001100011","0001110111","0001000110","0001010110","0001011111","0001100001","0001110100","0010011100","0010101100","0001101111","0001100011","0001101001","0001110100","0001100000","0000011001","0000110101","0000000000"),
("0001001100","0001111000","0001000101","0001011000","0001011011","0001100011","0001111000","0010011111","0010110010","0010101111","0001111000","0001010000","0010000001","0000101100","0000100100","0001111100","0000000000"),
("0001010010","0001111100","0001000101","0001100000","0001100000","0001100110","0010000101","0010011000","0010011111","0010100100","0010011111","0010100011","0010100111","0000100101","0001011111","0010001000","0000000000"),
("0001010101","0010000000","0001000100","0001100100","0001110110","0001101001","0001101100","0001011111","0001100000","0010010011","0010101001","0010011100","0001010110","0000110011","0010000110","0010000011","0000000000"),
("0001010110","0001111111","0001000100","0001011001","0001111011","0001010111","0000110001","0000101001","0001110100","0010100100","0010000101","0001010000","0000011011","0001011101","0010001101","0010000011","0000000000"),
("0001010010","0010000000","0001001000","0001011011","0001011100","0000101010","0000100001","0001101100","0001111100","0010011100","0010000010","0000101110","0000100111","0001111101","0010000100","0001111010","0000000000"),
("0001001011","0010000010","0001001110","0001010111","0000111001","0000100100","0001001000","0001111001","0001100001","0010000011","0001010001","0000110000","0001000100","0010000100","0001111100","0010000100","0000000000"),
("0000111010","0010000000","0001010011","0001000000","0000101001","0000111000","0001010000","0001101110","0010001001","0010000011","0001100101","0000110001","0001100011","0001111110","0010000110","0010110000","0000000000"),
("0000111010","0010000100","0001001010","0000111000","0001000100","0001001110","0000101101","0001100111","0001110111","0010000001","0001000001","0000110111","0001111011","0001111000","0010011111","0010111101","0000000000"),
("0000110001","0010001000","0001000001","0000111001","0001011111","0000110010","0000011101","0001001001","0001110011","0001101010","0000011100","0001000011","0001111111","0001110110","0010101110","0010110001","0000000000"),
("0001000011","0010000010","0000110110","0000110001","0001010010","0000110011","0000011010","0000111100","0001110100","0010001101","0001100000","0001000101","0001101101","0001101000","0010100001","0001001100","0000000000"),
("0001010011","0010000010","0000101101","0000100000","0001000000","0001000111","0000100100","0001010001","0001110011","0010001100","0010110010","0001101011","0001110010","0010001110","0001111110","0001000100","0000000000"),
("0001001111","0010000100","0000101100","0000011011","0000110101","0000101011","0000110010","0001100010","0001110011","0001111100","0010101001","0010001111","0001001111","0010001001","0001010100","0000111110","0000000000"),
("0001011101","0010000100","0000100111","0000101001","0000110011","0000101000","0001001111","0001101101","0001110110","0001111000","0010010101","0010011111","0001001110","0001010111","0000111110","0000110110","0000000000"),
("0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000","0000000000"));

signal Bufftemp,Bufftemp1:Array2D;
begin

------ RP0
RP0: Process (clk)
variable i,j:integer range 0 to 7:=0;
variable temp2,temp1:signed(9 DOWNTO 0);
begin

if (clk' event and clk='1') then
i:=i+1;
if i>7 then
i:=0;
j:=j+1;
if j=8 then
j:=0;
end if;
end if;

temp1:=Im(2*j,2*i)+Im(2*j,2*i+2);
Bufftemp(2*j,2*i+1)<= Im(2*j,2*i+1) - 5;

BuffD_RP0(4*j+i)<=Bufftemp(2*j,2*i+1);

Bufftemp(2*j,2*i)<=Im(2*j,2*i)+ 5;

end if;
end process;

------ RP1---------

RP1: Process (clk)
variable i,j:integer range 0 to 7:=0;
variable Stemp,Dold,Dnew,temp2,temp1:signed(9 DOWNTO 0);
begin

if (clk' event and clk='1') then
i:=i+1;
if i>7 then
i:=0;
j:=j+1;
end if;

temp1:=Im(2*j+1,2*i)+Im(2*j+1,2*i+2);
Bufftemp(2*j+1,2*i+1)<= Im(2*j+1,2*i+1) - 5;

Bufftemp(2*j+1,2*i)<=Im(2*j+1,2*i)+ 5;
BuffD_RP1(4*j+i)<=Bufftemp(2*j+1,2*i);

end if;
end process;

end behave;

-- As you see i either use 2i, 2j with +1 or without it. So the same index in not repeated.
Altera_Forum
Honored Contributor
8 years ago
It makes it easier if you use code tags when posting code.

Second, you have a multiple driver error because i/j are not constant, and the compiler does not know that the array elements are not driven from multiple processes. You can only do this if the indeces are constants.
I recommend you drive all elements of an array from a single process (it will be less complicated and error prone anyway).
Altera_Forum
Honored Contributor
8 years ago
Iam driving it in two processes to fill them simultaneously to get more time. If I have to I will split the array to two arrays.

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No logic elements although I have an output

26 Replies

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