No clocks defined in design / Minimal verilog only example

Hi,

I've been stuck at this for two days.

First of I'm very new to Altera so this is probably something very

simple but I just can't figure/google this one out.

I've set up a simple project that compiles fine, except I get this "No clocks defined in design" error

and thus cannot get the Fmax for my trial design.

Obviously somehow the compiler does not understand that there is a clock used in

my Verilog code or something, but I cannot figure out what to do.

My verilog is like this:

//---------------------------------------------------------------------

module correlator(

input clk,

input sys_rst

);

<snip>

always @(posedge clk) begin

<snip>

//---------------------------------------------------------------------

This is my .qsf

//---------------------------------------------------------------------

set_global_assignment -name FAMILY "Arria 10"

set_global_assignment -name DEVICE 10AS066N3F40E2SG# set_global_assignment -name FAMILY "Cyclone 10 GX"

set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0

set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:57:02 JANUARY 17, 2018"

set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Pro Edition"

set_global_assignment -name TOP_LEVEL_ENTITY correlator

set_location_assignment PIN_G1 -to clk

set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id clocka

set_global_assignment -name DUTY_CYCLE 50 -section_id clocka

set_instance_assignment -name CLOCK_SETTINGS clocka -to clk

set_global_assignment -name BASED_ON_CLOCK_SETTINGS clocka -section_id clockb

set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id clockb

set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 2 -section_id clockb

set_global_assignment -name DUTY_CYCLE 50 -section_id clockb

set_global_assignment -name OFFSET_FROM_BASE_CLOCK "500 ps" -section_id clockb

set_global_assignment -name INVERT_BASE_CLOCK OFF -section_id clockb

set_instance_assignment -name CLOCK_SETTINGS clockb -to clkx2

set_instance_assignment -name MULTICYCLE 2 -from clk -to clkx2

//---------------------------------------------------------------------

In my .sdc I have:

//---------------------------------------------------------------------

create_clock -name {clk} -period 1.000 -waveform { 0.000 0.500 } [get_ports {clk}]

create_clock -name {clkx2} -period 1.000 -waveform { 0.000 0.500 } [get_ports {clkx2}]

//---------------------------------------------------------------------

I've copied those from the 'filtref' example from Quartus installation

and that project compiles fine and produces Fmax, but that project

has toplevel as schematic entry and I want/need Verilog/textfile only solution.

I've tried to find a complete example project that would be Verilog with

text only files but have not found one ... so a pointer would be highly

appreciated.

But the main question is how do I make Quartus recognize my clock?

wbr Kusti