No clocks defined in design / Minimal verilog only example

--- Quote Start ---

If your module was not the top level, and you connected the clock port to '1b1 or 1'b0, then it would be stuck at 1/0.

If this module is your top level, you've already assigned the clk port to a pin, so it will be connected correctly, (and not stuck at 1/0).

The lack of outputs is the problem. The compiler sees your design does nothing useful, and removes all the logic.

--- Quote End ---

Thanks! All of this is was the information that I could not find from the documentation and what I needed. With the outputs defined it now works a treat! Thanks again!