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Altera_Forum
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8 years ago

No clocks defined in design / Minimal verilog only example

Hi, I've been stuck at this for two days. First of I'm very new to Altera so this is probably something very simple but I just can't figure/google this one out. I've set up a simp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Your .sdc defines a clock targeting a port named clkx2 that does not exist in your code. Your .qsf shows clocks named clocka and clockb that aren't there either. I'm not sure what's going on here.