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Altera_Forum
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8 years ago

No clocks defined in design / Minimal verilog only example

Hi, I've been stuck at this for two days. First of I'm very new to Altera so this is probably something very simple but I just can't figure/google this one out. I've set up a simp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

check the warnings and ensure it hasnt removed all of your logic. This can often happen for several reasons:

- Clock not connected, or stuck at 1/0

- Reset always asserted

- Input logic stuck at specific value, causing design to be optimised awa

- Design having no effect on any outputs.

If you have no outputs in the design that can connect to pins, then the whole design will be optimised away.