No clocks defined in design / Minimal verilog only example

Thank you!

--- Quote Start ---

check the warnings and ensure it hasnt removed all of your logic. This can often happen for several reasons:

- Clock not connected, or stuck at 1/0

- Reset always asserted

If you have no outputs in the design that can connect to pins, then the whole design will be optimised away.

--- Quote End ---

Thanks, I was thinking along those lines. But this is where I need some hand holding.

Your write "If you have no outputs in the design that can connect to pins", this raises the question

how to ensure that "outputs can connect to pins" ?

Looking at my code I see that I actually have no outputs out of the module so indeed this can be the problem.

I will change, test and report back.

Your write " Clock not connected", this is also not clear to me how the clock should be connected,

if you look at my code this is all I have: I have a signal 'input clk' and 'always @(posedge clk)', what else do I need to do to

make the compiler understand that this is a clock.

I've not specified in anyway (or have I?) how that 'clk' is connected ... should I and how to do that?

Same confusion about the reset... as this is only meant as test case to gauge the FPGA speed and

the speed of that design I don't know where to connect those at this point and/or how to set them

so that I can get the Fmax out...

wbr Kusti