niosii + sdram connection problems

As you are using Nios II based system, you can use all the SOPC builder based components that are available with the SOPC Builder. I'm assuming that you are using CFI compliant flash memory. You can use the CFI Flash memory controller and SDRAM controller that are available with the SOPC Builder. To use CFI Flash memory controller (with Bi-directional IO), you'll need to use tri-state bridge component, which connects the bidirectional data bus with the avalon fabric's unidirectional data bus. The SDRAM controller can share this tri-state bridge or can be used independently. You need to use the tristate bridge for SDRAM only if the SDRAM shares the datapath with other tristate components on the board.

Hope this will help,

BD

Hello

I have a custom board where I 'm using a Cyclone EP1C6Q240C8N device, that has on board an external SRAM (16bits), ADC (16bits), and 2 DACs (16 bits) these devices share the data bus (16bits). My questions are the following:

Can I share the 16 bit bus with the above mentioned devices when I'm using the Sram to store the NIOS II program?

Has anybody has done something like this and have an example or at least

point me in the right direction?

I tried to make a custom SRAM component with tristated interface for SOPC builder but Nios does not recognized it, here is the component HDL.

module SRAM(

// Host Data

CSn,

OEn,

Wn,

Address,

BEn,

Data,

// SRAM

SRAM_CSn,

SRAM_OEn,

SRAM_Wn,

SRAM_Address,

SRAM_BEn,

SRAM_Data

);

// Host Side

input CSn;

input OEn;

input Wn;

inout [15:0] Data;

input [18:1] Address; // Altera documentation for external devices

input [1:0] BEn;

// SRAM Side

output SRAM_CSn;

output SRAM_OEn;

output SRAM_Wn;

inout [15:0] SRAM_Data;

output [17:0] SRAM_Address;

output [1:0] SRAM_BEn;

assign SRAM_Data = SRAM_Wn ? 16'hzzzz : Data;

assign Data = SRAM_Data;

assign SRAM_Address = Address;

assign SRAM_Wn = Wn;

assign SRAM_OEn = OEn;

assign SRAM_CSn = CSn;

assign SRAM_BEn = BEn;

endmodule

thanks in advance.

Hello :confused:!

I am trying to do the same thing(shared the SDRAM with NIOS processor), did you success! If you have any update please let me know,

Thanks

Hello Darifa

Here is an easy project where I"m sharing the bus with an ADC and SRAM, in

order to share the bus, I created a master to control the protocol to get readings from the adc ADS8371, this master is kind of a slave from the NIOS point of view, because it needs a reset signal off from the Nios to start sending the protocol to the adc to get the reading then once it get the data the master stores it in the SRAM.

Here is the archive file you can check it out, double click the master_one in the bdf file and you 'll find the verilog code for it and the system configuration in the SOPC file.

hope this help.

Regards

Oswako:)

Hello Oswako!

Thanks for the example, this will help a lot!

I did not try it yet!

Cheers,