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Altera_Forum
Honored Contributor
19 years agoniosii + sdram connection problems
I customized a FPGA developing borad based on nios ii, I get vhdl design modules of sdram and flash. but I got a problem: the nios ii generate cpu with vector ports like Addr[n-1..0],Data[n-1..0...
Altera_Forum
Honored Contributor
17 years agoHello
I have a custom board where I 'm using a Cyclone EP1C6Q240C8N device, that has on board an external SRAM (16bits), ADC (16bits), and 2 DACs (16 bits) these devices share the data bus (16bits). My questions are the following: Can I share the 16 bit bus with the above mentioned devices when I'm using the Sram to store the NIOS II program? Has anybody has done something like this and have an example or at least point me in the right direction? I tried to make a custom SRAM component with tristated interface for SOPC builder but Nios does not recognized it, here is the component HDL. module SRAM( // Host Data CSn, OEn, Wn, Address, BEn, Data, // SRAM SRAM_CSn, SRAM_OEn, SRAM_Wn, SRAM_Address, SRAM_BEn, SRAM_Data ); // Host Side input CSn; input OEn; input Wn; inout [15:0] Data; input [18:1] Address; // Altera documentation for external devices input [1:0] BEn; // SRAM Side output SRAM_CSn; output SRAM_OEn; output SRAM_Wn; inout [15:0] SRAM_Data; output [17:0] SRAM_Address; output [1:0] SRAM_BEn; assign SRAM_Data = SRAM_Wn ? 16'hzzzz : Data; assign Data = SRAM_Data; assign SRAM_Address = Address; assign SRAM_Wn = Wn; assign SRAM_OEn = OEn; assign SRAM_CSn = CSn; assign SRAM_BEn = BEn; endmodule thanks in advance.