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Altera_Forum's avatar
Altera_Forum
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19 years ago

niosii + sdram connection problems

I customized a FPGA developing borad based on nios ii, I get vhdl design modules of sdram and flash. but I got a problem: the nios ii generate cpu with vector ports like Addr[n-1..0],Data[n-1..0...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hello Oswako!

Thanks for the example, this will help a lot!

I did not try it yet!

Cheers,