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Altera_Forum's avatar
Altera_Forum
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18 years ago

niosii + sdram connection problems

I customized a FPGA developing borad based on nios ii, I get vhdl design modules of sdram and flash. but I got a problem: the nios ii generate cpu with vector ports like Addr[n-1..0],Data[n-1..0...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hello :confused:!

I am trying to do the same thing(shared the SDRAM with NIOS processor), did you success! If you have any update please let me know,

Thanks