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Altera_Forum
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18 years ago

niosii + sdram connection problems

I customized a FPGA developing borad based on nios ii, I get vhdl design modules of sdram and flash. but I got a problem: the nios ii generate cpu with vector ports like Addr[n-1..0],Data[n-1..0...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hello Darifa

Here is an easy project where I"m sharing the bus with an ADC and SRAM, in

order to share the bus, I created a master to control the protocol to get readings from the adc ADS8371, this master is kind of a slave from the NIOS point of view, because it needs a reset signal off from the Nios to start sending the protocol to the adc to get the reading then once it get the data the master stores it in the SRAM.

Here is the archive file you can check it out, double click the master_one in the bdf file and you 'll find the verilog code for it and the system configuration in the SOPC file.

hope this help.

Regards

Oswako:)