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Altera_Forum
Honored Contributor
Honored Contributorniosii + sdram connection problems
I customized a FPGA developing borad based on nios ii, I get vhdl design modules of sdram and flash. but I got a problem: the nios ii generate cpu with vector ports like Addr[n-1..0],Data[n-1..0...
Altera_ForumHonored Contributor
Honored ContributorIf you look under \altera\<version>\nios2eds\examples\<verilog or VHDL> you'll find designs for various development boards. All of those boards minus the 2c35 and 2s60 RoHS board use SDR SDRAM which you can use to apply to your own design. If you are using DDR SDRAM then you would want to look at the 2c35 or 2s60 RoHS designs.
