Honored ContributorHi,
There is a custom interface of NIOS with a device, having own DSP-Processor. Interface is 16-bit data bus. While reading the data NIOS is generating CSn and RD Enable twice. Please help me to resolve this problem. -- Regards, Chander
Honored ContributorHello,
what about bus width mismatch? A 32 bit read can turn in two 16 bit reads to consecutive addresses.Honored ContributorRead Write both are 16 bit.
Honored ContributorSo, Nios 2 has a 32 bit read/write port (one for read and one for write) while your device has an interface with 16 bits on the avalon bus. This is a mismatch, the interconnect fabric in SOPC builder will split the read or the write in two. Take a look at http://www.altera.com/literature/manual/mnl_avalon_spec.pdf, paragraph 3.6.1
--- Quote Start --- For example, when a 32-bit master port performs a read transfer from a 16-bit slave port, the system interconnect fabric executes two read transfers on the slave side on consecutive addresses, and presents 32-bits of slave data back to the master port --- Quote End --- If I understood correctly your situation, this may be a good cause for reading twice.Honored ContributorHi,
this is a flaw in the SOPC builder. The NIOS data master is a 32 Bit master. So accesses are always 32 bit, even if you do a 16 bit access. With 8 bit components it is even worse. The first or seond access to your 16 bit component (depending on the address) will have both byte enables disabled.Honored ContributorNot a flaw. It is declared in the Avalon Interface Specifications. Look my previous post.
Honored ContributorThe misunderstanding is related to the fact that NIOS always performs 32bit read accesses, even if you explicitly use IORD_16DIRECT or IORD_8DIRECT: in these cases you'll always get multiple CS and RD strobes.
This can be annoying if your external address is a fifo or some register which is supposed to change at every read access. The solution I used in a similar case is using a 32bit external data bus and connecting only the 8 or 16 bits I need; this way I always perform a single 32bit access and discard extra bits.Honored ContributorGabrigob you are right. But for me this is a flaw. Why executing two 16 bit transfers when only 16 bits are needed ? And one of the accesses is an "empty" access with byte enables disabeld. This increases access times unnecessarily.
Honored ContributorHi, Cris,
Thanks for your kind information, my issue get resolved. I took 32 bit bus from NIOS and mapped the Lower 16 bit with custom interface. Thanks a lot to all replies. --- Quote Start --- The misunderstanding is related to the fact that NIOS always performs 32bit read accesses, even if you explicitly use IORD_16DIRECT or IORD_8DIRECT: in these cases you'll always get multiple CS and RD strobes. This can be annoying if your external address is a fifo or some register which is supposed to change at every read access. The solution I used in a similar case is using a 32bit external data bus and connecting only the 8 or 16 bits I need; this way I always perform a single 32bit access and discard extra bits. --- Quote End ---
