nios-ii-on-die-temperature-sensor example

You can always regenerate the .sopcinfo file. They aren't interchangeable from design to design - the file describes the address map for a Qsys based system to the Eclipse tools. So what you need to do is launch Quartus. Then launch Qsys Tools -> Qsys. Then open the Qsys file (generally in the top directory of where you unpacked the design example). Then hit generate HDL, save and finish. Now you have the .sopcinfo file that correlates to the temperature sensor design that you can load into Eclipse. Best of luck.

Hi thanks for the reply, that solved the problem... Now everything is building in NIOSII. How ever when i try to run the project i get no messages in the console.

Got the debugger running...I deleted the projects i had in the workspace and now it seems runnnig...So now i can run code from NIOS-II in debugger mode via JTAG on the eval board :-)

You don't need the nios_setup.sip file to program the device. That file is a pointer to all the of the library files that you need to simulate your design. You do need the nios_setup.qip file that has a pointer to all of the files you need to map and fit your design. That file can always be regenerated the same way you generate the .sopcinfo file. Open up qsys ,read the .qsys file and generate HDL and you will find the .qip file. Make sure to use the Project --> add/remove files from project feature and add the .qip file in your design. This way the mapper/fitter knows where to look for the all IP files that make up your design project.

Hi

Hi the demo project on the on-die temperature, works fine on my eval Max10 board, but the temperature is off (Room temp is 22 deg C)

Which quartus version did you build your adc on? You might want to try on v14.1. It worked fine for me.

im on version 15.0 of quartus...can you have both versions (v15 and v14.1)installed at the same time ?

No problem for me. I had both the v14.1 & 15.0.

hi thanks for the tip on clock freq. In the demo there is one clock source@50MHz

    nios_setup u0 (
        .clk_clk                               (nios_50M_clk),//    clk.clk
        .reset_reset_n                         (reset_n),     //    reset.reset_n
        .led_io_external_connection_export        (LED),            //    led_pio_external_connection.export
        .sw_io_external_connection_export         (SW),             //     switch_pio_external_connection.export
        .modular_adc_0_adc_pll_clock_clk       (adc_10M_clk), //    modular_adc_0_adc_pll_clock.clk
        .modular_adc_0_adc_pll_locked_export   (pll_locked)   //     modular_adc_0_adc_pll_locked.export
    );

defparam        altpll_component.bandwidth_type = "AUTO",
        altpll_component.clk0_divide_by = 5,
        altpll_component.clk0_duty_cycle = 50,
        altpll_component.clk0_multiply_by = 1,
        altpll_component.clk0_phase_shift = "0",
        altpll_component.clk1_divide_by = 1,
        altpll_component.clk1_duty_cycle = 50,
        altpll_component.clk1_multiply_by = 1,
        altpll_component.clk1_phase_shift = "0",
        altpll_component.compensate_clock = "CLK0",
        altpll_component.inclk0_input_frequency = 20000,
        altpll_component.intended_device_family = "MAX 10 FPGA",
        altpll_component.lpm_hint = "CBX_MODULE_PREFIX=all_pll",
        altpll_component.lpm_type = "altpll",
        altpll_component.operation_mode = "NORMAL",
        altpll_component.pll_type = "AUTO",
        altpll_component.port_activeclock = "PORT_UNUSED",
        altpll_component.port_areset = "PORT_USED",
        altpll_component.port_clkbad0 = "PORT_UNUSED",
        altpll_component.port_clkbad1 = "PORT_UNUSED",
        altpll_component.port_clkloss = "PORT_UNUSED",
        altpll_component.port_clkswitch = "PORT_UNUSED",
        altpll_component.port_configupdate = "PORT_UNUSED",
        altpll_component.port_fbin = "PORT_UNUSED",
        altpll_component.port_inclk0 = "PORT_USED",
        altpll_component.port_inclk1 = "PORT_UNUSED",
        altpll_component.port_locked = "PORT_USED",
        altpll_component.port_pfdena = "PORT_UNUSED",
        altpll_component.port_phasecounterselect = "PORT_UNUSED",
        altpll_component.port_phasedone = "PORT_UNUSED",
        altpll_component.port_phasestep = "PORT_UNUSED",
        altpll_component.port_phaseupdown = "PORT_UNUSED",
        altpll_component.port_pllena = "PORT_UNUSED",
        altpll_component.port_scanaclr = "PORT_UNUSED",
        altpll_component.port_scanclk = "PORT_UNUSED",
        altpll_component.port_scanclkena = "PORT_UNUSED",
        altpll_component.port_scandata = "PORT_UNUSED",
        altpll_component.port_scandataout = "PORT_UNUSED",
        altpll_component.port_scandone = "PORT_UNUSED",
        altpll_component.port_scanread = "PORT_UNUSED",
        altpll_component.port_scanwrite = "PORT_UNUSED",
        altpll_component.port_clk0 = "PORT_USED",
        altpll_component.port_clk1 = "PORT_USED",
        altpll_component.port_clk2 = "PORT_UNUSED",
        altpll_component.port_clk3 = "PORT_UNUSED",
        altpll_component.port_clk4 = "PORT_UNUSED",
        altpll_component.port_clk5 = "PORT_UNUSED",
        altpll_component.port_clkena0 = "PORT_UNUSED",
        altpll_component.port_clkena1 = "PORT_UNUSED",
        altpll_component.port_clkena2 = "PORT_UNUSED",
        altpll_component.port_clkena3 = "PORT_UNUSED",
        altpll_component.port_clkena4 = "PORT_UNUSED",
        altpll_component.port_clkena5 = "PORT_UNUSED",
        altpll_component.port_extclk0 = "PORT_UNUSED",
        altpll_component.port_extclk1 = "PORT_UNUSED",
        altpll_component.port_extclk2 = "PORT_UNUSED",
        altpll_component.port_extclk3 = "PORT_UNUSED",
        altpll_component.self_reset_on_loss_lock = "OFF",
        altpll_component.width_clock = 5;
endmodule

	all_pll	alt_pll_inst (   .areset ( reset ),
	.inclk0 ( clk ),
	.c0 ( adc_10M_clk ),
	.c1 ( nios_50M_clk),
	.locked ( pll_locked )
	);