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Altera_Forum
Honored Contributor
Honored Contributornios-ii-on-die-temperature-sensor example
Hi
im totally new to FPGA's...Im trying to run the following example. http://www.alteraforum.com/forum/showthread.php?t=19108&highlight=on-die+temperature+sensor+example if i load the .pof file supplied all is good :-)... I would like to build&modify the c-code for the project as described in http://www.alterawiki.com/uploads/e/ec/nios_temp_sensor_design.pdf but i cant locate the nios_setup.sopcinfo file. I tried with eth_std_main_system.sopcinfo found at https://cloud.altera.com but then i get this error fatal error: altera_modular_adc_sequencer_regs.h: No such file or directory i cant find this .h file. thanks in advance /Stefan12 Replies
Altera_ForumThe lookup table for the ADC value and associated temperature in Celsius is here: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/max-10/ug_m10_adc.pdf (table 2-1). There is some curve fitting going on to cross reference the table to the lookup function. The value is store as alt_u8 (unsigned) so it must have been more intuitive for the code author to lookup positive values in the celsius_lookup_table array and then subtract 40 from the indexed value.
- Altera_Forum
Just wanted to check if this was the correct lookup table and why the - 40 ? is it some sort of offset ?. the 64 are from avg of 64 samples.
printf("\nOn-die temperature = %d, adc_avg = %d",(celsius_lookup(adc_avg/64-3417)-40),(adc_avg/64)); alt_u8 celsius_lookup(int adc_avg_in) { const alt_u8 celsius_lookup_table={ 165,165,165,164,164,164,163,163,163,162,162,162,161,161,161,160,160,160, 159,159,159,158,158,158,157,157,157,156,156,156,155,155,155,154,154,154, 153,153,152,152,152,151,151,151,150,150,150,149,149,149,148,148,148,147, 147,147,146,146,146,145,145,144,144,144,143,143,143,142,142,142,141,141, 141,140,140,140,139,139,138,138,138,137,137,137,136,136,136,135,135,135, 134,134,133,133,133,132,132,132,131,131,131,130,130,129,129,128,128,128, 128,127,127,126,126,126,125,125,125,124,124,124,123,123,122,122,122,121, 121,121,120,120,119,119,119,118,118,118,117,117,116,116,116,115,115,114, 114,114,113,113,113,112,112,111,111,111,110,110,109,109,109,108,108,107, 107,107,106,106,105,105,105,104,104,103,103,103,102,102,101,101,101,100, 100,99,99,99,98,98,97,97,96,96,96,95,95,94,94,94,93,93,92,92,91,91,91,90, 90,89,89,88,88,88,87,87,86,86,85,85,85,84,84,83,83,82,82,82,81,81,80,80, 79,79,78,78,78,77,77,76,76,75,75,74,74,73,73,73,72,72,71,71,70,70,69,69, 68,68,67,67,67,66,66,65,65,64,64,63,63,62,62,61,61,60,60,59,59,58,58,57, 57,56,56,55,55,55,54,54,53,53,52,52,51,51,50,50,49,49,48,48,47,47,46,46, 45,45,44,43,43,42,42,41,41,40,40,39,39,38,38,37,37,36,36,35,35,34,34,33, 33,32,31,31,30,30,29,29,28,28,27,27,26,26,25,24,24,23,23,22,22,21,21,20, 20,19,18,18,17,17,16,16,15,15,14,13,13,12,12,11,11,10, 9, 9, 8, 8, 7, 7, 6, 5, 5, 4, 4, 3, 2, 2, 1, 1, 0 }; return (celsius_lookup_table); } - Altera_Forum
hi thanks for the tip on clock freq. In the demo there is one clock source@50MHz
and the Altera Modular ADC core setting are as in the picture. http://www.alteraforum.com/forum/attachment.php?attachmentid=10801&stc=1 and setting from Quartus
is there a need for two clock sources ? PLL settings:nios_setup u0 ( .clk_clk (nios_50M_clk),// clk.clk .reset_reset_n (reset_n), // reset.reset_n .led_io_external_connection_export (LED), // led_pio_external_connection.export .sw_io_external_connection_export (SW), // switch_pio_external_connection.export .modular_adc_0_adc_pll_clock_clk (adc_10M_clk), // modular_adc_0_adc_pll_clock.clk .modular_adc_0_adc_pll_locked_export (pll_locked) // modular_adc_0_adc_pll_locked.export );defparam altpll_component.bandwidth_type = "AUTO", altpll_component.clk0_divide_by = 5, altpll_component.clk0_duty_cycle = 50, altpll_component.clk0_multiply_by = 1, altpll_component.clk0_phase_shift = "0", altpll_component.clk1_divide_by = 1, altpll_component.clk1_duty_cycle = 50, altpll_component.clk1_multiply_by = 1, altpll_component.clk1_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 20000, altpll_component.intended_device_family = "MAX 10 FPGA", altpll_component.lpm_hint = "CBX_MODULE_PREFIX=all_pll", altpll_component.lpm_type = "altpll", altpll_component.operation_mode = "NORMAL", altpll_component.pll_type = "AUTO", altpll_component.port_activeclock = "PORT_UNUSED", altpll_component.port_areset = "PORT_USED", altpll_component.port_clkbad0 = "PORT_UNUSED", altpll_component.port_clkbad1 = "PORT_UNUSED", altpll_component.port_clkloss = "PORT_UNUSED", altpll_component.port_clkswitch = "PORT_UNUSED", altpll_component.port_configupdate = "PORT_UNUSED", altpll_component.port_fbin = "PORT_UNUSED", altpll_component.port_inclk0 = "PORT_USED", altpll_component.port_inclk1 = "PORT_UNUSED", altpll_component.port_locked = "PORT_USED", altpll_component.port_pfdena = "PORT_UNUSED", altpll_component.port_phasecounterselect = "PORT_UNUSED", altpll_component.port_phasedone = "PORT_UNUSED", altpll_component.port_phasestep = "PORT_UNUSED", altpll_component.port_phaseupdown = "PORT_UNUSED", altpll_component.port_pllena = "PORT_UNUSED", altpll_component.port_scanaclr = "PORT_UNUSED", altpll_component.port_scanclk = "PORT_UNUSED", altpll_component.port_scanclkena = "PORT_UNUSED", altpll_component.port_scandata = "PORT_UNUSED", altpll_component.port_scandataout = "PORT_UNUSED", altpll_component.port_scandone = "PORT_UNUSED", altpll_component.port_scanread = "PORT_UNUSED", altpll_component.port_scanwrite = "PORT_UNUSED", altpll_component.port_clk0 = "PORT_USED", altpll_component.port_clk1 = "PORT_USED", altpll_component.port_clk2 = "PORT_UNUSED", altpll_component.port_clk3 = "PORT_UNUSED", altpll_component.port_clk4 = "PORT_UNUSED", altpll_component.port_clk5 = "PORT_UNUSED", altpll_component.port_clkena0 = "PORT_UNUSED", altpll_component.port_clkena1 = "PORT_UNUSED", altpll_component.port_clkena2 = "PORT_UNUSED", altpll_component.port_clkena3 = "PORT_UNUSED", altpll_component.port_clkena4 = "PORT_UNUSED", altpll_component.port_clkena5 = "PORT_UNUSED", altpll_component.port_extclk0 = "PORT_UNUSED", altpll_component.port_extclk1 = "PORT_UNUSED", altpll_component.port_extclk2 = "PORT_UNUSED", altpll_component.port_extclk3 = "PORT_UNUSED", altpll_component.self_reset_on_loss_lock = "OFF", altpll_component.width_clock = 5; endmodule
not sure what this is, should it be 50e6(50MHz) ? ? ? altpll_component.inclk0_input_frequency = 20000, /thanksall_pll alt_pll_inst ( .areset ( reset ), .inclk0 ( clk ), .c0 ( adc_10M_clk ), .c1 ( nios_50M_clk), .locked ( pll_locked ) ); - Altera_Forum
No problem for me. I had both the v14.1 & 15.0.
Btw, another thing that you can check is the Qsys clock, it should be 50Mhz or higher. While the ADC clock should be 10Mhz (or whatever as you declared in the ADC parameter and configured in your PLL). Dont confuse both of them. Otherwise, you may see weird stuffs like temperature reading at minus while it is actually at room temp. - Altera_Forum
im on version 15.0 of quartus...can you have both versions (v15 and v14.1)installed at the same time ?
- Altera_Forum
Which quartus version did you build your adc on? You might want to try on v14.1. It worked fine for me.
- Altera_Forum
Hi the demo project on the on-die temperature, works fine on my eval Max10 board, but the temperature is off (Room temp is 22 deg C)
raw adc 3732 -> -3 via lookup, is it just due to bad calibration ? Or has anybody experienced similar behavior - Altera_Forum
Hi
thank you very much, just what i needed...Got it running now.. - Altera_Forum
You don't need the nios_setup.sip file to program the device. That file is a pointer to all the of the library files that you need to simulate your design. You do need the nios_setup.qip file that has a pointer to all of the files you need to map and fit your design. That file can always be regenerated the same way you generate the .sopcinfo file. Open up qsys ,read the .qsys file and generate HDL and you will find the .qip file. Make sure to use the Project --> add/remove files from project feature and add the .qip file in your design. This way the mapper/fitter knows where to look for the all IP files that make up your design project.
In terms of including the NIOS executable in flash memory so you dont need to be tethered to a host computer, perhaps checkout this design example: https://cloud.altera.com/devstore/platform/15.0.0/nios-ii-adc-lcd-controller-design-example-10m50-dev-kit/ Look at the document link and search for the section that is called: Merging the NIOS executable into the FPGA configuration file . That will show you how to get the SW executable merged with hardware image and if stored on flash removes the requirement for a connection to a host computer. Let me know if that helps. - Altera_Forum
Got the debugger running...I deleted the projects i had in the workspace and now it seems runnnig...So now i can run code from NIOS-II in debugger mode via JTAG on the eval board :-)
I would like to burn it to flash but im having some problems. when i open the .par file from the on die temp example in Quartus v15, its missing the nios_setup.sip and the nios_setup.qip files so my "start compilation" (CTRL+L) fails in quartus. read about the elf2flash but cant get i to work, the flash programmer in v15 seem's to be missing some bottom compared to this 2-6 in this manual. https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_nios2_flash_programmer.pdf thanks in advance
