Newbie - Where to put my Time/Energy

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The application will be reading parallel output from a couple of high speed ADCs and processing that data into a serial stream.

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How fast (clock rate) and what signal processing are you doing with the data?

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I would like to start with the UART. I believe that I will require the NIOS processor to do computational manipulation of the data.

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Since you have a background in micros, this is probably a good place to start. Though you do not need to have a NIOS II processor as a master. The JTAG-to-Avalon-MM bridge allows you to read and write from an FPGA design via the USB interface.

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There are many paths that can take all my time like studying the avalon interface specifications etc. I have to be efficient with my time.

I am looking for advice on what would be a reasonable path to take to to get going to avoid heading down dead ends or "rabbit holes".

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Learn how to use Modelsim, and learn how to write testbenches.

You should use Modelsim and a testbench to check that each of the components you design work, and then integrate them into a larger system and check that they work there. The Avalon master can be your NIOS core, or it can be the Avalon-MM BFM (bus functional model - a simulation only component).

If you get stuck, just ask questions.

Cheers,

Dave

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How fast (clock rate) and what signal processing are you doing with the data?

Dave

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That is to be determined. The data will be IQ data from an RF front end and I am not sure what processing will be required. The ADCs will run between 15-20 MSPS.

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Since you have a background in micros, this is probably a good place to start. Though you do not need to have a NIOS II processor as a master. The JTAG-to-Avalon-MM bridge allows you to read and write from an FPGA design via the USB interface.

Dave

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This is good to know. I think I will try to get the UART working first without the NIOS uC. How would reccommend proceeding? SOPC tool to try to incorporate the UART with the JTAG-to-Avalon-MM bridge? Does that even make sense?

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Learn how to use Modelsim, and learn how to write testbenches.

You should use Modelsim and a testbench to check that each of the components you design work, and then integrate them into a larger system and check that they work there. The Avalon master can be your NIOS core, or it can be the Avalon-MM BFM (bus functional model - a simulation only component).

Dave

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OK, I have work to do. I am flying solo on this project and it is way overwhelming.

Thank you!

Rich

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If you get stuck, just ask questions.

Cheers,

Dave

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The data will be IQ data from an RF front end and I am not sure what processing will be required. The ADCs will run between 15-20 MSPS.

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This is quite 'slow' compared to what FPGAs can achieve. If you need multiple ADCs, with lots of bits, then you might want to consider using a JEDEC JESD204 ADC (NXP and TI have them). They multiplex the outputs onto LVDS or SERDES signals. You need a higher I/O rate FPGA, but you have less board routing and signal switching issues. The DE0 can be used for parallel output devices to start with.

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This is good to know. I think I will try to get the UART working first without the NIOS uC. How would reccommend proceeding? SOPC tool to try to incorporate the UART with the JTAG-to-Avalon-MM bridge? Does that even make sense?

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The components will both use the JTAG interface. I have not used the JTAG-UART, but you'd talk to that with the nios2-terminal program. The Avalon-MM master would be communicated with using SystemConsole. The Altera tools are bad when it comes to 'sharing' the JTAG interface, so you might run into issues. I'd say go for it ... if you have trouble, come back here and complain, and we can see what to try next.

Alternatively, you can talk to an FTDI UART (or another USB-to-Serial device, with the RS232 translators removed) via the DE0 I/O pins, and use the Avalon-MM master to talk to that. The FTDI FT245 module is about $20 on Digikey. That has a parallel output to the FPGA, but its pretty simple to interface to.

Cheers,

Dave

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This is quite 'slow' compared to what FPGAs can achieve. If you need multiple ADCs, with lots of bits, then you might want to consider using a JEDEC JESD204 ADC (NXP and TI have them). They multiplex the outputs onto LVDS or SERDES signals. You need a higher I/O rate FPGA, but you have less board routing and signal switching issues. The DE0 can be used for parallel output devices to start with.

The components will both use the JTAG interface. I have not used the JTAG-UART, but you'd talk to that with the nios2-terminal program. The Avalon-MM master would be communicated with using SystemConsole. The Altera tools are bad when it comes to 'sharing' the JTAG interface, so you might run into issues. I'd say go for it ... if you have trouble, come back here and complain, and we can see what to try next.

Alternatively, you can talk to an FTDI UART (or another USB-to-Serial device, with the RS232 translators removed) via the DE0 I/O pins, and use the Avalon-MM master to talk to that. The FTDI FT245 module is about $20 on Digikey. That has a parallel output to the FPGA, but its pretty simple to interface to.

Cheers,

Dave

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Thanks again Dave.

I am working with Qsys now, I have the uart_0, sys_clock, JTAG to avalon Master Bridge, and the JTAG UART. I have make connections as best I can.

What is left is the UART_0 external connection (Conduit endpoint), clk_in, and clk_reset. Clk_in, I presume gets connected to my 50 MHz oscillator. I am not sure about the others.

The UART_0 external connection must be the fifos, irqs, etc, correct? If these connections are left hanging in qsys do I connect them in my HDL code? Schematic entry?

Rich

Dave,

At this point I don't want to waste your time. I found another tutorial I will work through (tt_nios2_hardware_tutorial.pdf).

I am sure that I will be back!

Rich

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I am working with Qsys now, I have the uart_0, sys_clock, JTAG to avalon Master Bridge, and the JTAG UART. I have make connections as best I can.

What is left is the UART_0 external connection (Conduit endpoint), clk_in, and clk_reset. Clk_in, I presume gets connected to my 50 MHz oscillator. I am not sure about the others.

The UART_0 external connection must be the fifos, irqs, etc, correct? If these connections are left hanging in qsys do I connect them in my HDL code? Schematic entry?

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The top-level component clock and reset will connect to whatever your system clock and reset are supposed to be, eg. the 50MHz oscillator, and a reset push button (making sure to get the logic sense correct).

The JTAG connections are internal. I assume you have put a real UART in the design too, in that case connect RX and TX to I/O pins, or just create a signal at the top-level and loop them back on each other. That way you can write to the transmit register, and receive the character back.

Go through the tt_nios2_hardware_tutorial.pdf to get familiar with things, and then come back to your design.

Cheers,

Dave

Will do, thanks again.

Rich

I worked my way through the tutorial, no problems till I got to the code development on the Eclipse based tool. It almost worked, various errors when trying to download to the chip. I was using an eclipse workspace that is shared by other tools I use, ARM, MSP430 etc. Creating a new workspace just for the Altera/Nios stuff fixed it.

I managed to delete the JTAG UART and replace it with a generic UART and got that to work through the DE0 UART hardware. :-) (small victories...)

I still have no idea how to do any timing analysis, need to study that. Need to keep studying Verilog.

I am not sure how to implement large parallel IO ports and to translate them to a buffer. These would come from ADCs and there would be, I assume, some sort of clock and strobe signals...

A lot of this feels very dubious in that developing this way is SO dependent of fixed software tools, so much of it consists of "black boxes". I worry that if something breaks I will not be able to fix it. Like the random error messages from the Eclipse tool that I eventually fixed by creating a new workspace.

I am used to microcontrollers where the hardware is fixed and I have my choice of many tools.

I am also concerned about IP pricing. The Altera website is TERRIBLE, why don't the have a simple pricing matrix?

Rich

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I worked my way through the tutorial, no problems till I got to the code development on the Eclipse based tool. It almost worked, various errors when trying to download to the chip. I was using an eclipse workspace that is shared by other tools I use, ARM, MSP430 etc. Creating a new workspace just for the Altera/Nios stuff fixed it.

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I don't use NIOS in any of my designs, and I don't use IDEs (rather I prefer to command line tools, where I have complete control).

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I still have no idea how to do any timing analysis, need to study that.

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For a simple processor with on-chip RAM and slow PIO, all you really need is a clock constraint.

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I am not sure how to implement large parallel IO ports and to translate them to a buffer. These would come from ADCs and there would be, I assume, some sort of clock and strobe signals...

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For an ADC interface, you'd use I/O registers, and then pipeline the data into your signal processing logic.

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A lot of this feels very dubious in that developing this way is SO dependent of fixed software tools, so much of it consists of "black boxes". I worry that if something breaks I will not be able to fix it. Like the random error messages from the Eclipse tool that I eventually fixed by creating a new workspace.

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You can always ditch the GUI. It basically comes down to how confident you are in the tools, versus your own skills. You could choose to ignore the NIOS processor and focus on the FPGA hardware side of things too.

Take a step back and consider this as the 'first pass' through the design phase. During this first pass, you are identifying what works, what does not, and what needs more work. If the NIOS stuff is not working for you, move on, and come back to it later.

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I am used to microcontrollers where the hardware is fixed and I have my choice of many tools.

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You're in a whole new world now :)

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I am also concerned about IP pricing. The Altera website is TERRIBLE, why don't the have a simple pricing matrix?

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I don't think you'll find pricing without contacting an FAE.

Cheers,

Dave

Dave,

Thank you again for the valuable advice. I think you are right, however I end up using (or not using) the tools, this is the easiest way in.

I am still not sold on the need for the FPGA and time/money is of the essence. I think an ARM micro running at 120MHz may be just fine. I will have to do some number crunching to find out.

I will be a bit disappointed if the micro is ok as I am interested in learning technology that is new to me....

Rich