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This is quite 'slow' compared to what FPGAs can achieve. If you need multiple ADCs, with lots of bits, then you might want to consider using a JEDEC JESD204 ADC (NXP and TI have them). They multiplex the outputs onto LVDS or SERDES signals. You need a higher I/O rate FPGA, but you have less board routing and signal switching issues. The DE0 can be used for parallel output devices to start with.
The components will both use the JTAG interface. I have not used the JTAG-UART, but you'd talk to that with the nios2-terminal program. The Avalon-MM master would be communicated with using SystemConsole. The Altera tools are bad when it comes to 'sharing' the JTAG interface, so you might run into issues. I'd say go for it ... if you have trouble, come back here and complain, and we can see what to try next.
Alternatively, you can talk to an FTDI UART (or another USB-to-Serial device, with the RS232 translators removed) via the DE0 I/O pins, and use the Avalon-MM master to talk to that. The FTDI FT245 module is about $20 on Digikey. That has a parallel output to the FPGA, but its pretty simple to interface to.
Cheers,
Dave
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Thanks again Dave.
I am working with Qsys now, I have the uart_0, sys_clock, JTAG to avalon Master Bridge, and the JTAG UART. I have make connections as best I can.
What is left is the UART_0 external connection (Conduit endpoint), clk_in, and clk_reset. Clk_in, I presume gets connected to my 50 MHz oscillator. I am not sure about the others.
The UART_0 external connection must be the fifos, irqs, etc, correct? If these connections are left hanging in qsys do I connect them in my HDL code? Schematic entry?
Rich
Honored Contributor
