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I am working with Qsys now, I have the uart_0, sys_clock, JTAG to avalon Master Bridge, and the JTAG UART. I have make connections as best I can.
What is left is the UART_0 external connection (Conduit endpoint), clk_in, and clk_reset. Clk_in, I presume gets connected to my 50 MHz oscillator. I am not sure about the others.
The UART_0 external connection must be the fifos, irqs, etc, correct? If these connections are left hanging in qsys do I connect them in my HDL code? Schematic entry?
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The top-level component clock and reset will connect to whatever your system clock and reset are supposed to be, eg. the 50MHz oscillator, and a reset push button (making sure to get the logic sense correct).
The JTAG connections are internal. I assume you have put a real UART in the design too, in that case connect RX and TX to I/O pins, or just create a signal at the top-level and loop them back on each other. That way you can write to the transmit register, and receive the character back.
Go through the tt_nios2_hardware_tutorial.pdf to get familiar with things, and then come back to your design.
Cheers,
Dave
Honored Contributor
