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How fast (clock rate) and what signal processing are you doing with the data?
Dave
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That is to be determined. The data will be IQ data from an RF front end and I am not sure what processing will be required. The ADCs will run between 15-20 MSPS.
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Since you have a background in micros, this is probably a good place to start. Though you do not need to have a NIOS II processor as a master. The JTAG-to-Avalon-MM bridge allows you to read and write from an FPGA design via the USB interface.
Dave
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This is good to know. I think I will try to get the UART working first without the NIOS uC. How would reccommend proceeding? SOPC tool to try to incorporate the UART with the JTAG-to-Avalon-MM bridge? Does that even make sense?
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Learn how to use Modelsim, and learn how to write testbenches.
You should use Modelsim and a testbench to check that each of the components you design work, and then integrate them into a larger system and check that they work there. The Avalon master can be your NIOS core, or it can be the Avalon-MM BFM (bus functional model - a simulation only component).
Dave
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OK, I have work to do. I am flying solo on this project and it is way overwhelming.
Thank you!
Rich
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If you get stuck, just ask questions.
Cheers,
Dave
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